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sn28837 1/2-inch pal timer socs031b july 1991 copyright ? 1991, texas instruments incorporated 1 post office box 655303 ? dallas, texas 75265 ? pal-timing operation ? solid-state reliability ? color and monochrome operation ? five selectable-antiblooming modes ? variable-integration-time option ? surface-mount package ? clamp-pulse select option ? horizontal and vertical resets for external synchronization description the sn28837 is a monolithic integrated circuit designed to supply timing signals for the texas instruments (ti ? ) 8-mm-diagonal tc276 (pal color) and tc277 (pal monochrome) ccd image sensors. the sn28837 supplies both ccd-drive signals and pal-television synchronization signals at standard video rates. it requires a single 5-v supply voltage and a 13.37-mhz crystal-oscillator input. the sn28837 provides the user with several options including multiple antiblooming modes, variable-integration time, external synchronization, clamp-pulse selection, and delayed horizontal transfer. the sn28837 is designed to drive the ccd image sensor through intermediary level-shifting devices such as the ti tms3473b parallel driver and the sn28846 serial driver. it also supplies sample-and-hold signals for the ti tl1593 3-channel sample-and-hold circuit and multiplex signals for the ti tl1051 video preprocessor. in color applications, the sn28837 interfaces with the sn28838 color-subcarrier generator to generate the pal color subcarrier. the sn28837 is supplied in a 60-pin plastic flat package and is characterized for operation from 20 c to 45 c. this device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fie lds. these circuits have been qualified to protect this device against electrostatic discharges (esd) of up to 2 kv according to mil-std-8 83c, method 3015; however, precautions should be taken to avoid application of any voltage higher than maximum-rated voltages to the se high-impedance circuits. during storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. in a circuit, unused inputs should always be connected to an appropriate logic voltage level, preferably eithe r v cc or ground. specific guidelines for handling devices of this type are contained in the publication guidelines for handling electrostatic-discharge-sensitive (esds) devices and assemblies available from texas instruments. ti is a trademark of texas instruments incorporated. v cc v cc1 x2 x1 gnd v cc pi abin gt ps nc s3 s2 s1 t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 bcp1 bcp2 cp1 cp2 csync cblk bf vd scblk idp hgate testa fi sfi nc 17 18 19 20 21 22 23 24 25 26 27 28 29 59 58 57 56 55 54 53 52 51 50 49 48 47 hcr vcr gt2 sh1 clk pd lsw clk13m nc gt3/sh2 nc nc gt1/sh3 16 30 nc 46 gnd 60 testc vds high gps gp vd2 abs1 abs2 abs0 vgate nc testb e/l v cc sb fs package (top view) nc no internal connection production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
sn28837 1/2-inch pal timer socs031b july 1991 2 post office box 655303 ? dallas, texas 75265 functional block diagram oscillator divide by 4 13 mhz 3.3 mhz horizontal counter vertical counter clock generator antiblooming generator serial generator decoder 49 37 39 36 31 pd gt pi ps t s1 s2 s3 sh1 gt3/sh2 gt1/sh3 gt2 32 33 34 51 53 56 57 38 abin gps gp vds sb abs0 abs1 abs2 21 22 23 e/l 19 hcr 59 vcr 58 x1 42 x2 43 50 clk 47 clk13m 26 27 18 29 1 2 3 4 5 6 7 8 48 9 10 12 16 17 28 20 11 12 14 bcp1 bcp2 cp1 cp2 csync cblk bf vd lsw scblk idp testa testb testc vd2 vgate hgate fi sfi
the levels on these three terminals determine which of the five antiblooming modes is selected: mode abs2 abs1 abs0 operation 0 nc l l no abg pulses 1 nc h l 2-mhz burst of abg pulses 2 nc l h 1-mhz burst of abg pulses 3 h h h 1-mhz continuous abg pulses 4 l h h 2-mhz continuous abg pulses sn28837 1/2-inch pal timer socs031b july 1991 3 post office box 655303 ? dallas, texas 75265 terminal functions terminal i/o description name no. i/o description abin 38 o antiblooming in abs0 21 i abs1 22 i abs2 23 i mode 1 is used for normal operation. bcp1 1 o optical black clamp bcp2 2 o optical black clamp bf 7 o burst flag cblk 6 o composite blank clk 50 o 3.34-mhz clock (factory-test point) clk13m 47 o 13-mhz clock (connect to sn28838 color-subcarrier generator for color operation) cp1 3 o clamp 1 (signal processing) cp2 4 o clamp 2 (signal processing) csync 5 o composite sync e/l 19 i delay select for s1, s2, s3. when e/l is high, the three serial-transfer pulses occur early relative to the sample-and-hold pulses sh1, sh2, and sh3. when e/l is low, the three serial-transfer pulses occur late relative to the sample-and-hold pulses. fi 13 o field index gnd 41, 60 ground gp 27 i exposure control: gp gates the ps and pi outputs (see the description of gps) gps 26 i when gps is high, the timer operates in the normal-integration-time mode (t int = 20 ms) and vd is connected internally to gp. to operate the imager in the variable-integration-time mode, gps must be held low and a user-defined logic circuit must be inserted between vd and gp to vary the integration time (see figure 1). gt 37 o tms3473b parallel-driver midsel input switch gt1/sh3 56 o gt1/sh3 is a logic signal for both y gate 1 of the tl1051 video preprocessor and sample-and-hold channel 3 of the tl1593 3-channel sample-and-hold circuit. gt2 57 o y gate 2 for the tl1051 video preprocessor gt3/sh2 53 o gt3/sh2 is a logic signal for both y gate 3 of the tl1051 video preprocessor and sample-and-hold channel 2 of the tl1593 3-channel sample-and-hold circuit. hcr 59 i horizontal-counter reset hgate 11 o decoded h count signal. hgate is a test point and is not used in normal operation. high 25 i not used (tie high) idp 10 o id pulse (for secam operation) lsw 48 o line switch (connect to sn28838 for color operation) nc 15, 30, 35, 46, 52, 54, 55 no connect pd 49 o power down. a low-logic level on pd causes the device to enter a low power-consumption mode. pi 39 o parallel-image-area gate clock ps 36 o parallel-storage-area gate clock sb 29 i standby-mode select. when sb is high, normal operation is selected; when sb is low, the power-down mode is selected. scblk 9 o subcarrier blank (for secam applications)
sn28837 1/2-inch pal timer socs031b july 1991 4 post office box 655303 ? dallas, texas 75265 terminal functions (continued) terminal i/o description name no. i/o description sfi 14 o second field index sh1 51 o sample and hold 1 s1 32 o serial clock 1 s2 33 o serial clock 2 s3 34 o serial clock 3 t 31 o transfer-gate clock testa 12 o test a (factory-test point) testb 16 o test b (factory-test point) testc 17 o test c (factory-test point) v cc 24, 40, 45 dc power vcc1 44 oscillator power vcr 58 i vertical-counter reset vd 8 o vertical drive vds 18 i vertical-dump speed. when vds is high, the vertical-dump frequency is 3.3 mhz; when vds is low, the vertical-dump frequency is 2 mhz. vd2 28 o real-display-area signal. vd2 is a test point and is not used in normal operation. vgate 20 o decoded v count signal. vgate is a test point and is not used in normal operation. x1 42 crystal oscillator (see figure 2) x2 43 cr y stal oscillator (see fig u re 2) 12 3 t int flush pulses transfer pulse gp figure 1. gp flush and transfer pulses
sn28837 1/2-inch pal timer socs031b july 1991 5 post office box 655303 ? dallas, texas 75265 variable-integration-time mode in addition to the normal tv mode of operation, the sn28837 timing generator offers an optional variable-integration mode for use with the tc276 and tc277 ccd area-array image sensors. the variable-integration mode is selected by applying a low-logic level to gps. this low-logic level disables the vertical-drive (vd) signal from controlling, internal to the timer, the image-area and storage-area parallel transfer signal (gp). prior to the start of a new integration period, the charge that has accumulated in the image area must be transferred out. to flush this previous signal or dark-current charge from the image area, gp is pulsed low two times. each low pulse generates 302 pulses image-area and storage-area gate and transfer signals that shift the unwanted charge into the clearing drain. this clearing function should be performed during the high time of the vd signal (see figure 3 through figure 13). the new integration period continues as long as gp remains high. gps must be held at a low-logic level to prevent vd from controlling gp internally. the integration ceases and the readout occurs when vd and gp are pulsed low simultaneously; this is accomplished by taking gps to a high-logic level. the readout timing is dependent on the vertical-drive pulse; this means that the total-integration time is a multiple of 1/50 of a second plus the time interval between the last gp low pulse and the next vd low pulse. the image readout occurs within the normal 1/50-second readout interval. if the integration time is less than 1/50 of a second, normal output operation occurs; if the integration time is greater than 1/50 of a second, a frame buffer may be required to capture the image. integration times greater than 1/50 of a second result in image degradation at temperatures greater than 25 c due to dark-current generation. the degradation is seen as a decrease in dynamic range (contrast) and an increase in noise. it is recommended that the image sensor be cooled for long-exposure operation. the dark-current generation is reduced by a factor of two for each 7 c temperature decrease. the sensor operates at 30 c. cooling can be accomplished by using a thermoelectric or peltier cooler attached to the image sensor. condensation on the header must be prevented by isolating the cooled sensor from moist air. vacuum isolation is preferred; however, the continual flushing of dry nitrogen across the header can also prevent condensation. x1 x2 42 43 c1 40 pf c2 40 pf sn28837 note: the sn28837 is designed for use with a crystal oscillator. the x1 and x2 terminals should not connect directly to external driver outputs. figure 2. connection of an external crystal oscillator to the sn28837
sn28837 1/2-inch pal timer socs031b july 1991 6 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v dd (see note 1) 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i 0.3 v to v dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o 0.3 v to v dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous total power dissipation at (or below) t a = 25 c 300 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a 20 c to 45 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 55 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 in) from case for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to gnd. recommended operating conditions min nom max unit supply voltage, v dd 4.5 5 5.5 v high-level input voltage, v ih v dd x 0.7 v low-level input voltage, v il 0.8 v operating frequency 13.375 mhz power-up time 300 m s operating free-air temperature, t a 20 45 c electrical characteristics over recommended operating ranges of supply voltage and free-air temperature (unless otherwise noted) 3 parameter test conditions min typ max unit v oh gt3/sh2 and gt1/sh3 v dd = 4.5 v, i oh = 4 ma 3.5 v v oh all other outputs v dd = 4.5 v, i oh = 2 ma 3.5 v v ol gt3/sh2 and gt1/sh3 v dd = 4.5 v, i ol = 4 ma 0.5 v v ol all other outputs v dd = 4.5 v, i ol = 2 ma 0.5 v i ih v ih = 5 v 1 m a i il v il = 0 30 200 500 m a i dd(av) average supply current 10 30 ma i dd(s) standby supply current 1 ma 3 the hcr, sb , and vcr inputs are schmitt-trigger inputs with 0.1-v to 1-v hysteresis. all inputs except x1 have pullup-current sources. switching characteristics over recommended operating free-air temperature range, v dd = 5 v parameter test conditions min typ max unit f clock frequency s1, s2, s3, sh1, gt2, gt1/sh3, gt3/sh2 c l =50 p f 4.458333 mhz t w pulse duration s1, s2, s3, sh1, gt2, gt1/sh3, gt3/sh2 c l = 50 pf 75 ns t rise time gt1/sh3 and gt3/sh2 10 ns t r rise time all other outputs c l =50 p f 50 ns t f fall time gt1/sh3 and gt3/sh2 c l = 50 pf 10 ns t f fall time all other outputs 50 ns
sn28837 1/2-inch pal timer socs031b july 1991 7 post office box 655303 ? dallas, texas 75265 bf vertical scale abin gt1/sh3 sh1,gt3/sh2, gt2 s1,s2,s3 hgate cblk 1262 1265 1260 1254 1255 1270 1278 1286 1294 1302 1310 1862 1870 1878 1886 1894 1902 1910 1918 1926 lsw 1875 1924 1925 1872 1298 1248 1248 1250 1300 1875 1248 1276 1872 1900 1937 1245 1312 1870 1314 1939 1314 1867 1248 1872 1298 1924 1276 1250 1874 1900 vgate vd2 bcp2 bcp1 cp2 cp1 sf1 f1 idp scblk vd csync 1243 1242 1256 1874 1890 1875 1250 1892 1910 1890 1885 1880 1875 1925 1250 1250 1250 1248 1268 1872 1892 1875 1875 1890 1265 1268 1268 1286 1286 1300 1300 1892 1910 1925 eq vs eq eq vs eq 1246 1238 2h 4th field 1st field 1875 always continuous ps, t gt pi notes: a. gps is low and vd is fed back to gp. b. when gps is high, vgate is always low. c. 1 field = 312 1/2 horizontal lines = 625 vertical counts. 1 frame = 625 horizontal lines = 1250 vertical counts. period of ea ch count of vertical counter = 32 m s. figure 3. vertical timing (first and fourth fields)
sn28837 1/2-inch pal timer socs031b july 1991 8 post office box 655303 ? dallas, texas 75265 2h 625 0 vertical scale 0 0 2488 2492 2496 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 612 616 620 624 628 625 3rd field 2nd field 632 636 640 644 648 652 656 660 664 668 672 676 50 675 2496 16 620 640 15 625 18 36 50 625 642 660 675 18 36 642 660 0 15 2498 16 640 676 050 625 625 675 2498 48 622 674 2498 26 622 650 2493 2495 62 64 618 620 687 689 2492 64 617 689 csync cblk bf vd lsw scblk idp fi sfi cp1 cp2 bcp1 bcp2 vd2 vgate always continuous hgate pi gt 2498 48 622 674 ps,t ab in 0 26 624 624 650 0 26 624 650 s1,s2,s3 sh1, gt1/sh3, gt3/sh2 gt2 eq eq vs eq eq vs notes: a. gps is low and vd is fed back to gp. b. when gps is high, vgate is always low. c. 1 field = 312 1/2 horizontal lines = 625 vertical counts. 1 frame = 625 horizontal lines = 1250 vertical counts. period of ea ch count of vertical counter = 32 m s. figure 4. vertical timing (second and third fields)
sn28837 1/2-inch pal timer socs031b july 1991 9 post office box 655303 ? dallas, texas 75265 horizontal scale 2 sh1,gt3/sh2, gt1/sh3 gt2 s1,s2,s3 hsync 4 08 212 208 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 96 100 104 108 112 116 120 124 cp2 bcp2 bcp1 scblk 5 200 196 192 clk continuous (214) 21 eq 513 11 2 vs 5 203 96 204 120 11 2 cblk 040 bf 23.5 31 lsw 5 5 024 048 521 038 30 34 30 34 5 112 hgate ps 24 28 t 04 8121620 4 8 12 16 20 24 see note a cp1 idp csync 2 for the horizontal scale (t1 clock), one interval = 299 ns 4 master-clock periods. notes: a. although s1, s2, and s3 appear to be coincident, s1 leads s2 by t5 ns, and s2 leads s3 by 75 ns between 4 and 24 on the horizontal scale. b. 1 tv line = 64 m s = 214 horizontal clocks figure 5. horizontal timing
sn28837 1/2-inch pal timer socs031b july 1991 10 post office box 655303 ? dallas, texas 75265 4.458333-mhz pulse cp2 bcp2 bcp1 sw-y output ch3 ch2 ch1 s/h output gt2 ch3 ch2 ch1 ccd output gt1/sh3 gt3/sh2 sh1 s3 s2 s1 cblk (1):not for use, (2):half-dark, da:dark, du:dummy, a:active 10 9 8 7 6 5 4 3 2 1 a 12 11 10 9 8 7 6 5 4 3 2 1 21 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 da 1 da 2 da 3 da 4 da 5 da 6 da 7 du 1 du 2 du 3 du 41 a 2 a 3 a 4 4 3 2 1 4 3 2 1 7 6 5 4 3 2 a a a (2)a du du du du da da da da da da 0(1) 1 da t1 = 299 ns 40 39 38 37 36 35 34 33 32 31 30 29 28 horizontal scale dark dummy active 19 20 note a: this chart shows early mode only. late mode is shown in figure 7. figure 6. s, sh, gt timing (start of h)
sn28837 1/2-inch pal timer socs031b july 1991 11 post office box 655303 ? dallas, texas 75265 gt2 gt1/sh3 gt3/sh2 sh1 s2 s3 s1 s3 s2 s1 t1 29 30 early late 5 ns 5 ns 5 ns 37.4 10 ns 5 ns 5 ns 5 ns 10 ns(s1/sh1) 5 ns 5 ns 5 ns 5 ns 5 ns t1 = 299 ns note a: s1, s2, s3, sh1, gt3/sh2, gt1/sh3, gt2 are: cycle time = 224.3 ns pulse width = 74.8 ns duty cycle = 1/3 figure 7. s, sh, gt waveforms
sn28837 1/2-inch pal timer socs031b july 1991 12 post office box 655303 ? dallas, texas 75265 t1 active sw-y output s/h output ch1 ch2 ch3 a 232 233 da 1 da 1 all outputs are held until next pulse until next pulse all outputs are held da 1 da 1 233 232 a ch3 ch2 (214) 0 213 212 211 ch1 gt2 ccd output gt1/sh3 gt3/sh2 sh1 s3 s2 s1 cblk t1 = 299 ns note a: this chart shows early mode only. late mode is shown in figure 7. figure 8. s, sh, gt timing (end of h)
sn28837 1/2-inch pal timer socs031b july 1991 13 post office box 655303 ? dallas, texas 75265 2t1 h counter(t1) 206 208 210 0 2 4 6 8 10121416 1820222426 2830 3234363840 42 44 mode 1 2-mhz burst 212 cblk bcp1 bcp1 mode 2 1-mhz burst mode 3 mode 4 vd intgo abclr (mode 1, mode 2) v timing abin abin (mode 1, mode 2) h timing t1 = 299 ns 1 mhz (0.9554 mhz) 2 mhz (1.9107 mhz) always free running antiblooming mode selection mode abs0 abs1 abs2 abin output 0 x 0 0 no abg 1 x 1 0 2 mhz burst 2 x 0 1 1 mhz burst 3 1 1 1 1 mhz const 4 0 1 1 2 mhz const x = don't care notes: a. for mode 1 and mode 4, duty cycle is 4/7 high and 3/7 low. b. only the timing from odd field to even field is shown. the timing from even field to odd field is the same as that for odd fi eld to even field minus the h-to-v timing. c. gps is always high. figure 9. abin timing
sn28837 1/2-inch pal timer socs031b july 1991 14 post office box 655303 ? dallas, texas 75265 vd (see note a) ps,t pi power sb (see note a) powerup operation normal operation sb s1,s2,s3 abin pd gt vd (see note c) ps,t pi s1,s2,s3 abin gt see note d 1026 pulses refresh pulse (see note b) 290 pulses 290 pulses 290 pulses 1026 pulses refresh pulses (see note b) notes: a. a capacitor is connected to sb (between sb and gnd). b. refresh pulses (1026 pulses) of pi, ps and t are generated even if vd is not fed back to gp. c. vd is always fed back to gp and gps is low. d. pi, ps, s1, s2, s3, abin, and gt go low when sb is low. figure 10. operation chart of sb
sn28837 1/2-inch pal timer socs031b july 1991 15 post office box 655303 ? dallas, texas 75265 vd gp pi ps,t gt abin bcp1, bcp2 mode operation (see note b) 302 pulses (see note a) 290 pulses clear operation normal operation notes: a. when vd is low and gp goes low, 290 pulses are generated for pi, ps, and t after vd goes high. b. when vd is high, gp goes low and 302 pulses are generated for pi, ps and t. c. gps is at a steady-state low level. figure 11. normal timing and variable integration h counter n n+1 n+2 m m+1 m+2 m+3 6 7 n+3 clk t1 = 299 ns 89 n+4 m m+1 m+2 m+3 6 7 8 9 hcr (see note a) h counter(t1) cblk hcr (see note b) reset window notes: a. the h counter is preset to the value 6 when hcr changes from low to high. b. output signals are changed one t1 clock after the change of the counter through the output latches. figure 12. operation of hcr
sn28837 1/2-inch pal timer socs031b july 1991 16 post office box 655303 ? dallas, texas 75265 v counter (see note a) n n+1 n+2 m m+1 m+2 m+3 16 17 n+3 clk 1h = 64 m s 18 19 n+4 m m+1 m+2 m+3 16 17 18 19 vcr v counter (see note a) clk vcr reset window note a: the v counter is preset to the value 16 when vcr changes from low to high. figure 13. operation of vcr
sn28837 1/2-inch pal timer socs031b july 1991 17 post office box 655303 ? dallas, texas 75265 mechanical data this plastic package consists of a circuit mounted on a lead frame and encapsulated within an electrically nonconductive plastic compound. the compound withstands soldering temperatures with no deformation, and circuit performance characteristics remain stable when operated in high-humidity conditions. the package is intended for surface mounting, and leads are spaced on 1,0-mm centers with a 0,8-mm foot length. leads require no additional cleaning or processing when used in soldered assembly. index corner fs060 all linear dimensions are in millimeters and parenthetically in inches 15 16 60 1 15,0 (0.591) nom detail a 0 12 see detail a chamfer 18,2 (0.717) 17,4 (0.685) 0,65 (0.026) 0,45 (0.018) 14,2 (0.559) 13,8 (0.543) 31 45 0,20 (0.008) 0,10 (0.004) 1,4 (0.055) 0,8 (0.031) 0,10 (0.004) min seating plane designation per jedec std 30: pqfp-g44 2,1 (0.083) 1,9 (0.075) 46 30 0,95 (0.037) 0,65 (0.026) (44 pin used for illustration to save space) 7/94
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1998, texas instruments incorporated

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